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preliminary publication release date may 2003 - 1 - revision 3.09 wts701 winbond single-chip text-to-speech processor the information contained in this dat asheet may be subject to change without notice. it is the responsibility of the cu stomer to check the winbond usa website ( www.winbond-usa.com ) periodically for the latest version of this document, and any errata sheets that may be generated between datasheet revisions.
wts701 - 2 - 1. general description the wts701 is a high quality, fully integrated, single- chip text-to-speech solution that is ideal for use in applications such as automotive appliances, gps/navigation systems, cellular phones and other portable products or accessories. the wts 701 product accepts ascii (unicode and big5 for mandarin) input via a spi port and converts it to spoken audio via an analog output or digital codec output. the wts701 integrates a text processor, smoothi ng filter and multi-level memory storage array on a single-chip. text-to-speech conversion is achieved by processing the incoming text into a phonetic representation that is then mapped to a corpus of naturally spoken word parts. the synthesis algorithm attempts to use the largest possible word unit in the appropriate context to maximize natural sounding speech quality. the speech units are stored uncompressed in a multi-level, non-volatile analog storage array to provide the highest sound qualit y to density trade-off. this unique, single-chip solution is made possible through winbond?s patent ed multilevel storage technology. voice and audio signals are stored directly into solid-state memory in their natural, uncompressed form, providing superior quality voice reproduction. the chip can be programmed through the spi por t, allowing downloading of different languages and speaker databases when made available by winbond.
wts701 publication release date: may 2003 - 3 - revision 3.09 2. features ? fully integrated solution single-chip compact text-to-speech translation no algorithm development required selectable digital and analog audio output simple spi interface reprogrammable solution enables loading different voice or language ? text-to-speech algorithm characteristics high quality speech synthesis usi ng speech element concatenation winbond?s standard 100-year speech retention audio stored as uncompressed analog waveform ? i ndustry?s highest quality and most natural sounding ? easy to use and control real time conversion for streaming text general text preproc essing and normalization user customization for special characters such as sms icons and chat emoticons user customization for applic ation specific abbreviations ? language support support u.s. english and m andarin (beijing dialect) other languages in development or in planning ? device management accepts ascii, unicode or big5 streaming text 256-byte text buffer playback of phonetic alphabet variable speed playback control of pitch change supports power down mode. supports pause and resume, stop and fi nish text conversion commands embedded characters support to control speed, vo lume, case sensitivity, and silent behavior ? peripheral control 16-bit linear pcm slave interface output support spi serial port for control commands and st atus report to system?s host controller hardware handshake control signals analog audio output with 8 ? speaker driver, digital volume control and line level o/p analog audio input (auxin) for drivi ng external audio to the speaker ? low power consumption +2.7 to +3.3v (v cc ) supply voltage operating current: i cc convert = 35 ma (typical) standby current: i sb < 1 a (typical) ? device characteristics available in 56-lead tsop package industrial temperature range (-40c to +85c) 3v/5v logic tolerance
wts701 - 4 - 3. block diagram 3.1. wts701 b lock d iagram aux out v ssa v cca v ss a v ssd v ssd v ccd v ccd power conditioning ram flash codestore memory (rom) sp i inte rface reference generation mls phoeneme memory high voltage generation processor 13 bit codec linear/ 2?s complement ss\ mosi miso sclk mls control log ic vclk vdx vfs sp+ sp- spkr. amp aux out amp clock generation xtal1 xtal2 analog signal condition ing auxin aux amp r/b\ int\ reset cs\ att cap figure 1. wts701 block diagram.
wts701 publication release date: may 2003 - 5 - revision 3.09 3.2. wts701 t ypical a pplications figure 2. wts701 configuration fo r digital (codec) environment. figure 3. wts701 configuration for analog environment host controller wts701 ss\ mosi miso sclk vdx vclk vfs sp+ sp- auxin r/b\ int\ cs\ auxout baseband processor codec din cl fs dout host controller wts701 ss\ mosi miso sclk vd x vclk vfs sp+ sp- auxin r/b\ int\ cs\ auxout lin e out lin e in
wts701 - 6 - 4. table of contents 1. general d escription......................................................................................................... ......... 2 2. features .................................................................................................................... ..................... 3 3. block diagram ............................................................................................................... ............... 4 3.1. wts701 bl ock di agram ...................................................................................................... ......... 4 3.2. wts701 typica l applic ations ............................................................................................... ........ 5 4. table of cont ents ........................................................................................................... ........... 6 5. pin conf igurati on ........................................................................................................... ............ 8 6. pin des cription ............................................................................................................. ................ 9 7. functional descript ion...................................................................................................... .... 11 7.1 text-to-s peech mec hanism ................................................................................................... .... 12 7.1.1 text no rmalizat ion ....................................................................................................... ......... 12 7.1.2 words-to-phonem e conver sion ............................................................................................ 12 7.1.3 phonem e mappi ng .......................................................................................................... ...... 12 7.2 physical interf ace ......................................................................................................... ............... 13 7.2.1 clocking requirem ents .................................................................................................... ..... 13 7.2.2 power down mode.......................................................................................................... ...... 14 7.2.3 power and groundi ng ...................................................................................................... ..... 14 7.2.4 spi in terface ............................................................................................................ ............. 15 7.2.5 flow cont rol inte rface ................................................................................................... ........ 16 7.2.6 the code c interf ace ...................................................................................................... ..... 16 7.2.7 the anal og interf ace..................................................................................................... ........ 17 7.2.8 re setting ................................................................................................................ ............... 18 7.3 communicati on prot ocol..................................................................................................... ......... 19 7.3.1 command classe s.......................................................................................................... ...... 20 7.3.2 status regi ster.......................................................................................................... ............ 21 7.3.3 interr upt h andler ........................................................................................................ ........... 22 7.3.4 bcnt -- byte count r egister.............................................................................................. .. 23 7.3.5 command accept ance....................................................................................................... ... 23 7.3.6 data acceptance.......................................................................................................... ......... 23 7.4 commands overvi ew .......................................................................................................... ........ 23 7.4.1 command descrip tion ...................................................................................................... .... 26 7.4.2 illegal comm ands ......................................................................................................... ........ 37 7.4.3 configurat ion regi sters .................................................................................................. ...... 37 7.4.4 system operat ion ......................................................................................................... ........ 41 7.4.5 initialization and configur ation......................................................................................... ..... 43
wts701 publication release date: may 2003 - 7 - revision 3.09 7.4.6 conver ting text.......................................................................................................... ........... 43 7.5 spi in terface .............................................................................................................. .................. 46 7.5.1 spi tr ansacti ons......................................................................................................... .......... 46 7.6 codec in terface............................................................................................................ ............. 49 7.7 control charac ters......................................................................................................... .............. 52 7.7.1 phonetic al phabet play back ............................................................................................... .. 52 7.7.2 s peed c hange ............................................................................................................. ......... 54 7.7.3 volu me c hange ............................................................................................................ ........ 55 7.7.4 case s ensitivity......................................................................................................... ............ 55 7.7.5. paus e cont rol ........................................................................................................... ........... 55 7.8 customizing abbrevia tions .................................................................................................. ........ 56 7.8.1 abbreviati on data format ................................................................................................. .... 56 7.8.2 abbreviati on table format................................................................................................ .... 57 7.8.3 command execution........................................................................................................ ..... 57 7.9 device progra mming ......................................................................................................... .......... 58 7.10 text-to-speech processor commm ands ? quick refe rence t able........................................ 59 7.10.1 text i nput fo rmat....................................................................................................... ......... 64 7.10.2. buffer length limit .................................................................................................... ........... 65 7.10.3. undefi ned charac ters ................................................................................................... ...... 65 8. timing wavefor ms ............................................................................................................ ......... 66 8.1 spi timi ng diagr am......................................................................................................... ............ 66 8.2 codec timi ng diagr ams ...................................................................................................... ..... 68 9. absolute maxi mum ratings.................................................................................................... 70 10. electrical cha racteris tics ............................................................................................... 71 11. typical applic ation ci rcuit ................................................................................................ .74 12. package drawing and dimens ions .................................................................................... 75 13. ordering informat ion....................................................................................................... .... 76 14. version history ............................................................................................................ ........... 77
wts701 - 8 - 5. pin configuration the following sections detail the pins of the wts701 processor. table 1 shows all the pins and the signals that use them in different configurations. it also shows the type and direction of each signal. figure 4 shows the physical pin out of the 56-pin tsop package. 1 2 3 4 5 6 7 8 9 10 11 12 13 vssa wts701 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 vclk vfs vdx miso xt al2 xt al1 vssd vssd vccd vccd int \ mosi ss\ sclk nc nc nc nc nc nc nc nc nc nc 56 cs\ r/b\ reset auxout auxin vcca sp+ vssa sp- attcap nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc vssa figure 4. 56-pin tsop package connection diagram.
wts701 publication release date: may 2003 - 9 - revision 3.09 6. pin description table 1. wts701 pin signal assignment. pin no. symbol i/o function 2,36,44 vssa g analog ground pins. 3 vclk i codec master clock 4 vfs i codec frame synchronization signal 5 vdx o codec data output. this pin puts data out in the linear pcm unsigned or 2?s complement format. it is tri-stated until the user requests a convert operation. 6 miso o spi m aster i n, s lave o ut pin. serial data line used to communicate with spi master. pin is tri-state when ss =1. 7 xtal2 o crystal 2: this is t he crystal oscillator output. it is the inversion of xtal1. 8 xtal1 i crystal 1: this is the cr ystal oscillator input. this pin may be driven by an external clock. t he clock to the wts701 processor is configured by a clock configurat ion register, which is set by the host processor during the initialization phase. 9,10 vssd g digital ground pin. 11,12 vccd p positive digital voltage supply pin. these pins carry noise generated by internal clocks in the chip. they must be independently bypassed to digital ground to ensure correct device operation and not connected together. 13 int o interrupt output; an open drain out put that indicates that the device wishes an interrupt serv ice. the device can request an interrupt when it finishes an operation or needs more data to process. under what conditions the device generates an interrupt can be configured through the user configuration registers. this pin remains low until a read interrupt command is executed. 14 mosi i spi m aster o ut, s lave i n. serial data input from master and open drain 15 ss i spi slave select input. this is an active low input used to select the device to respond to an spi transaction. 16 sclk i spi serial clock input. 25 cs i chip select (active low) pin must be low to access wts701 device. 26 r/ b o ready/busy signal; this pin defaul ts high indicating the device is ready for data transfer. the pin is driven low to handshake a pause in spi data transfer and open drain.
wts701 - 10 - pin no. symbol i/o function 27 reset i global reset signal. 40 attcap i/o automute capacitor pin. should have a 4.7uf capacitor to v ssa . 42 sp- o differential negative speaker driver output. 46 sp+ o differential positive speaker driver output. 48 vcca p positive analog voltage supply pin. this pin supplies the low level audio sections of the device. it should be carefully bypassed to analog ground to ensure correct device operation. 52 auxin i analog input pin. this pi n should be capacitively coupled. see page 73 for example. 54 auxout o analog output for si ngle ended output from the device. 1,17- 24,28- 35,37- 39,41,43, 45,47,49- 51,53,55- 56 nc not connected ? must be floating. note: type i:input, o:output, i/o bi-directional, p:power, g:ground
wts701 publication release date: may 2003 - 11 - revision 3.09 7. functional description as a real system-on-chip solution, the wts701 performs the overall control functions for host controller and text-to-speech processing. the wts701 system architecture c onsists of the following functions: ? serial interface to monitor the spi port and interpret commands and data ? text normalization module to pre-proce ss incoming text into pronounceable words ? words to phoneme translator, which conv erts incoming text to phoneme codes ? phoneme mapping module that maps incoming phonemes to words, sub-words, syllables or phonemes present in the mls memory ? volume and speed adjustments ? digital and analog output blocks for off-chip usage the wts701 system performs text -to-speech synthesis based on conc atenative samples. the units for concatenation can vary from whole words dow n to phoneme units. the convention is that the larger the sub-word unit used for synthesis the hi gher the quality of the speech output. a corpus of pre-recorded words is stored in winbond?s patent ed multilevel storage (mls) memory and a mapping of the various sub-word parts is held in a l ookup table. the speech creation is achieved by concatenation of these speech elements to produce wo rds. the system process flow is shown in figure 5. text normalization words to phoneme phoneme mapper mls memory digital output analog output wts701 speech serial text, symbols & control figure 5. wts701 system process flow.
wts701 - 12 - 7.1 t ext -t o -s peech m echanism the text to speech component of the sy stem consists of three principal blocks: ? text normalization ? word to phoneme conversion ? phoneme mapping 7.1.1 text normalization text normalization involves the translation of inc oming text into pronounceable words. it includes such functions as expanding abbreviations and translating numer ic strings to spoken words. it involves a certain amount of context processing to determine correct spoken form. in addition, the wts701 looks into the abbreviation list stored in the device?s internal memory and converts acronyms, abbreviations or special characters (such as instant messaging icons or emoticons) into the appropriate text representation. the default abbreviation list supported by the wts 701 is a general one that cannot be modified by the user to match the domain that the text is being loaded from. but the default list can be overridden by the user abbreviation list. this enables a flexibility of adding abbreviation specifically for the text either by the developer or even the end user to best cust omize the product for its preferences. instant messaging or short messages service (sms) unique characters are supported through this functionality as well, defining the icon, ascii/unic ode/big5 text, and its replacement. the default abbreviation list supported is described in the specific language release letter . 7.1.2 words-to-phoneme conversion once the data stream has been translated to pr onounceable words, the system next determines how to pronounce them. this function is obviously highly language dependent. for a language such as english it is impossible to break this task down to a set of definitive rules. the task is achieved by a combination of rule based processing t ogether with exception processing . 7.1.3 phoneme mapping this algorithm maps phoneme strings into the ml s phonetic inventory. this task falls into two portions. first, the word must be split into s ub-word portions. this splitting must be done at appropriate phonetic boundaries to achieve high quality c oncatenation. once a sub-word unit is determined, the inventory is searched to determ ine if a match is present. a matching weight is assigned to each match depending on how closely the phonet ic context matches. each sub-word has a left and right side context to match as well as the phoneme string itself. if no suitable match is found in the inventory, then the sub-word is further s plit in a tree like manner until a match is found. the splitting tree is processed from left to right and each time a successful match occurs the address and duration of the match in the corpus is placed in a queue of phonetic parts to be played out the audio interface.
wts701 publication release date: may 2003 - 13 - revision 3.09 7.2 p hysical i nterface the following sections describe the physical pin propert ies and the timing associated with the physical interface to the device. note that all input pins are 3v and 5v tolerant, except for the cs signal which is only 3v tolerant. 7.2.1 clocking requirements the wts701 processor can receive its clock from either an external clock source or a crystal oscillator. the xtal1 and xtal2 pins provide the cryst al interface to the device. the clock to the wts701 processor is configured by a clock configur ation register, which must be set by the host processor during the initialization phase. figure 6 below shows how to connect the wts701 to a crystal oscillator. an external clock can be connect ed to the wts701 providing the clock source for the system, as shown in figure 6. wts701 xtal1 xtal2 wts701 xtal1 xtal2 clk in x1 c1 c2 c1 = c2 = 15pf x1 = 24.576mhz figure 6. clock generation. suggested crystal specification: f = 24.576 mhz fundamental mode operation c l = 16 pf esr = 60 ? maximum
wts701 - 14 - 7.2.2 power down mode upon application of power, the wts701 will enter the reset state and then be in a power down state. in the power down mode, only cla ss0 spi commands are valid. (see subsection 7.3.1 ). the power down status of the device can be deter mined with a rdst (read status) command, specified by the rdy bit in status byte 0. issuing the pwdn (power down) command to the wts 701 processor will return the processor to the power down mode. in power down mode the external crystal oscillator is shut off and the processor is deactivated. power down mode is exited by issuing a pwup (power up) command to the wts701. the pwup command should be pr eceded by a sclc (set clock) command to ensure correct clock configuration. 7.2.3 power and grounding the wts701 can operate over 2.7v to 3.3v s upply voltage range. the power supply and ground pins (v cca , v ccd , v ssa , v ssd ) should be carefully bypassed as close to the chip as possible to ensure high quality audio. in addition, attcap pin should have a 4.7 f capacitor connected to ground. this pin must not be left floating. the pins that are mark ed as nc (not connected), must be left floating. v cca , v ccd (voltage inputs) to minimize noise, the analog and digital circuits in t he wts701 device use separate power busses. these +3.0 v busses lead to separate pins. for optimal noise immunity, tie the v ccd pins together as close as possible and decouple both supplies as near to the package as possible. v ssa , v ssd (ground inputs) the wts701 series utilizes separate analog and digital ground busses. the analog ground (v ssa ) pins should be tied together as close to the package as possible and connected through a low- impedance path to power supply ground. the digital ground (v ssd ) pin should be connected through a separate low-impedance path to power supply ground. these ground paths should be large enough to ensure that the impedance between the v ssa pins and the v ssd pin is less than 3 ? . the backside of the die is connected to v ssd through the substrate resistance. nc (not connect) these pins must not be connected to the board at any time. connection of these pins to any signal, ground or v cc may result in incorrect device behav ior or cause damage to the device.
wts701 publication release date: may 2003 - 15 - revision 3.09 7.2.4 spi interface communications with the wts701 is conducted over the spi serial communications port. the device responds to a command when the chip select signal ( cs ) is low and addressed by an active low signal on the ss (slave select) pin. under this condition, it accepts data on the mosi input, which is clocked in on rising edges of the serial clock (sclk) signal. concurrently, v alid data from the wts701 device to the bus master is available on miso for the high period of sclk. the protocol implemented on the wts701 defines that the first two bytes of data sent in an spi transaction is a command word. a transaction is defined as the spi transfers conducted while ss is low, the transaction ends when ss returns high. a list of available commands can be found in subsection 7.10 (text-to-speech processor commands quick re ference table). the data flow over the spi interface is msb first, both in and out of the wts701. all input pins are 3v and 5v tolerant, except for the cs signal which is only 3v tolerant. the following is a description of the wts701 spi interface signals: sclk (serial clock) the serial clock line is a digital input. it is driven by t he spi master and controls the timing of the data exchanged over the spi data lines, mosi and miso. the maximum frequency for this pin is 5 mhz. ss (slave select) the slave select line is an active low digital input. it is driven by the spi master and acts as a chip select line. the device only responds to spi trans actions when this line is selected (low) and then raised high after spi communication ends. cs (chip select) the chip select line is an active low digital input. it can be driven by the host controller to enable spi transactions to the device. normally this pin is tied low unless more than one device is to share the same ss signal. mosi (master out, slave in) the mosi line is a digital input. mosi is driven by t he spi master. it provides data transfer, msb first, from the master to the slave. (see page 64) miso (master in, slave out) the miso line is an open drain digital output. when ss is high, this pin is tri-state. when ss is low, miso is driven by the device. it provides ser ial data transfer, msb first, from the slave to the master.
wts701 - 16 - 7.2.5 flow control interface in addition to the spi interface, the wts701 has tw o control lines to facilitate data transfer and host communications. the int (interrupt) pin is used by the wt s701 to request an interrupt service from the host controller. the interrupt types that the device generates are controlled by the communications control register command (scom). the r/ b (ready/busy) pin is used to control the flow of data across the spi bus. when this signal is high, the device can accept more data. when it is low, spi transactions must be paused or terminated. int (interrupt) int is an open drain output pin. the wts701 inte rrupt pin goes low and stays low when an interrupt event has occurred, as defined by the scom command. the interrupt is cleared when a rint (read interrupt) command is ex ecuted. the status register defines what type of interrupt has occurred. r/ b (ready/busy signal) the r/ b line is an output open drain pin used to control data transfer rate across the spi port. the line is used as a handshake signal to the spi master to indicate when the device is ready for more data. when high, the master is free to send mo re data. when low, the device is busy and cannot accept more data. 7.2.6 the codec interface the wts701 provides an on chip interface for digit al environment systems, supporting slave codec interface mode. the wts701 codec interface is controlled by an external source hence the wts701 only transmits data. thus, it is effect ively an analog-to-digital converter. each analog sample is converted to 10 bit digital word. this digital word is transmitted with the msb first. since the host expects either 13 or 16 bit data in the short fram e format, either three or six zeros are appended as the lsb. it interfaces to the baseband codec via the vclk, vfs and vdx lines. refer to figure 2 , for more information about the connec tion between the wts701 and a codec. all input pins are 3v and 5v tolerant. the following is a description of the wts701 codec interface signals: vclk (codec clock line) the codec clock line supplies the sampling clock to the internal codec. this is a digital input and expects a 512khz?2.048mhz clock.
wts701 publication release date: may 2003 - 17 - revision 3.09 vfs (codec synchronization line) the codec synchronization line supplies a frame sync hronization signal to the internal codec. this is a digital input. after receipt of a synchronization pulse, the codec will output data on the vdx line. the vfs line expects an 8khz sample rate and supports both short frame and long frame synchronization signal. vdx (codec data transmit line) the codec data transmit line is a digital output that places digital audio data onto the codec bus. the line is in a tri-state condition until the device is due to transmit data. the data output from the vdx line is selected by the scod command. when wts 701 places data on the vdx line, it is required that the vfs line should be in tri-state condition when another device is connected to the codec as well. 7.2.7 the analog interface the wts701 provides an on-chip analog interface for audio output via an 8 ? speaker driver or an output buffer capable of driving a 5k ? load. additionally, an analog input (auxin) allows an audio signal to be fed through the wts701 chip to either output device. the command saud configures the analog path. a digitally controlled attenuator provides volume control via the svol command. the following is a description of the analog pins: auxin (analog input) the auxin is an additional audio input to the wts701. this input has a nominal 694 mv p-p level at its minimum gain setting (0 db) (see table 2 ). additional gain is available in 3 db steps (controlled by the saud command) up to 9 db. the use and equivalent circuit of the input amplifier is shown in figure 7. (must be ac coupled) ra internal to the device rb c coup = 0.1 f 1 2 r a c coup note: f cutoff = figure 7. auxin input amplifier.
wts701 - 18 - table 2. auxin gain settings. aud register 0tlp input v p-p 1 aig1 aig0 gain 2 gain 2 (db) resistor ratio (r b /r a ) speaker out v p-p 3 0.694 0 0 1.00 0 40.1 / 40.1 1.388 0.491 0 1 1.41 3 47.0 / 33.2 1.388 0.347 1 0 2.00 6 53.5 / 26.7 1.388 0.245 1 1 2.82 9 59.2 / 21 1.388 1 otlp input is the reference transmission level point that is used for testing. this level is typically 3 db below clipping. 2 from auxin to auxout. 3 measured differentially at sp+/sp-. auxout (analog output) the auxout is an audio output pin used to provide an analog output of the synthesized speech from the wts701. it drives a minimum load of 5 k ? up to a maximum of 1 v p-p . the ac signal is superimposed on approximately 1.2 vdc bias and must be capacitively coupled to the load . this output stage may be powered down by clearing the aopu bit via the saud command. sp +, sp- (speaker +/-) this is the speaker differential output circuit. it is designed to drive an 8 ? speaker connected across the speaker pins up to a maximum of 23.5 mw power. this stage has selectable gains of 1.32 and 1.6, which can be chosen through the spg bit v ia the saud command. these pins are biased to ap- proximately 1.2 vdc and, if used single-ended, mu st be capacitively coupled to their load. do not ground the unused pin. this output stage may be pow ered down by clearing the sppu bit via the saud command. attcap (automute attenuator capacitor) this pin provides a capacitor connection for setting the automute. it should have a 4.7 f capacitor connected to ground and it cannot be left floating. the automute circuit reduces the amount of noise present in the output during quiet pauses. 7.2.8 resetting the chip has an internal power-on reset circuit that ensures correct initialization upon application of power. the reset pin signal must be held high for 0.5 s to achieve a reset (see figure 8 ) and to put the wts701 in the reset state. once the wts701 completes the reset, it will enter the power down mode. before issuing active commands, a clock configuration and device power up command must be issue in the power down mode. issuing a reset command (rst) resets the wts701 processor to the initial power down state. applying the reset pin, while the chip is active, allows the host processor to reset the wts701 to its default values and the idle state.
wts701 publication release date: may 2003 - 19 - revision 3.09 t res et t res et > 0.5 s reset figure 8. reset condition timing. 7.3 c ommunication p rotocol the wts701 is controlled by a series of spi tr ansactions to send commands to the device. the general format of an spi transaction is shown in figure 9. a transaction is always started by sending a command word. the command word consists of a command byte followed by a command data byte. at the same time, the status register is shi fted out on the miso line. what follows depends on what command is sent. the general case is that following the command word, up to n -bytes of data can be sent to the device and n- bytes can be read from the device. an spi transaction is finished when ss is returned to the high condition. datan data1 datan data1 data0 data0 cmd data status byte 1 cmd byte status byte 0 mosi miso msb lsb time 7 7 7 7 7 77 7 0000 0000 figure 9. spi transaction format.
wts701 - 20 - 7.3.1 command classes the spi transactions to the wts701 fall into four c lasses. the four classes represent variations in how the command, and any associated data, is handled. the class of a command is defined by the two most significant bits of the command byte. a summary of the command classes is given below class 0 commands these are commands that are executed irrespective of the state of the wts701. that is, the command will execute even if the device is busy or powered down. these commands are executed internally by a hardware command interpreter. all co mmands not of class 0 require that the wts701 be in a powered up state. example of class 0 co mmand is the read status (rdst) command. class 1 commands class 1 commands require interpretation by the inter nal firmware of the wts701. class 1 commands consist only of a command byte and command data by te. any further data sent in a transaction is ignored. class 1 commands are most often used fo r setting a configuration register in the device or sending commands that have no data such as the conversion pause (paus) command. class 2 commands class 2 commands have associated data. after the command word, any data bytes following are loaded into an internal fifo buffer for processing. if this fifo becomes full, the r/ b signal is asserted (low) indicating that the host must pause data transfer. an alternative to monitoring the r/ b line, the r/ b bit of the status register c an be monitored instead (see subsection 7.3.2 ) or via the rdst command. the r/ b bit cannot be used for intra-byte flow c ontrol, e.g. if a string of characters is sent, only every other byte is checked. class 3 commands class 3 commands have data to return to the host. the r/ b line will go to busy immediately following the command word indicating that the wts701 is fe tching the requested data. data is put into the bcnt0 and bcnt1 (see subsection 7.3.4 ) registers and is read out in the two subsequent bytes after r/ b is released. if more than two bytes are returned from the command, r/ b will again be asserted until data is ready to read. the primary class 3 commands are to read the contents of internal configuration registers such as rreg command.
wts701 publication release date: may 2003 - 21 - revision 3.09 7.3.2 status register the wts701 has a sixteen-bit status register whose value is returned to the host controller during the command word. for class 2 commands, the status r egister is repeatedly returned every two bytes. this status register provides the host with informa tion regarding the current status of the chip. the host can decide on required actions wi th this information. the status register is echoed back by all commands. table 3. status bytes. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 status byte 0 icnt ibuf icnv cod bful bemp cnvt rdy status byte 1 r/ b reserved reserved reserved reserved iabb reserved icmd the contents of the status bytes are described in table 4 .
wts701 - 22 - table 4. status bit description. byte bit name bit # rdy 0 ready to accept commands. after the device has been powered up, this bit is set after the power up latency delay. cnvt 1 converting. this bit is set any time while the conversion process is running. if this bit is clear when a c onvert command is sent, the count in the count register is set to 0. bemp 2 the text input buffer is empty. this bit is set anytime the input buffer is empty. bful 3 the text input buffer is full. this bit is cleared after 128 bytes become available in the input buffer. cod 4 codec is enabled. this is set when the codec has been enabled by the scod command. icnv 5 conversion finished interrupt has occurred. to stop codec transmission or power down the analog outputs an idle command should be sent. this bit is cleared by rint command. ibuf 6 the input text buffer been filled above the defined threshold and then gone below the defined threshold. the buffer threshold level is set by the scom command. if set by the scom command, the int pin will also go low. this bit is cleared by rint command. status byte 0 icnt 7 count interrupt has occurred. t his interrupt is generated every time a word has been spoken if activated by the scom command. this bit is cleared by rint command. icmd 0 command was ignored. anytime icmd is set, the transaction must revert to a single word command and the command must be resent. any data sent will be ignored. iabb 2 abbreviation interrupt has o ccurred, abbreviation add or abbreviation delete has been completed. now the enter_rrsm command can be sent. status byte 1* r/ b 7 current state of the r/ b pin. if this bit is 0, any data sent will be ignored. *5 bits are reserved. 7.3.3 interrupt handler if an interrupt has occurred, no further interrupts will be registered until the first interrupt has been cleared. only one interrupt can be active at any time. the rint command will read and clear pending interrupts while the rdst command will read interrupts without clearing them. make sure that all interrupts that are not being used are masked by clearing the corresponding bits in the com register.
wts701 publication release date: may 2003 - 23 - revision 3.09 7.3.4 bcnt -- byte count register the byte count register (bcnt) is a tool for the host to keep track of where in a conversion the wts701 is. when a new conversion is started, the byte count register is reset to zero. as each word (as defined by white-space separated characters) is spoken, the byte count register is updated to point to the first character of the next word to be spoken. in this way, the host can position a new conversion if the user wishes to repeat or skip tex t. the bcnt register is sent with bcnt1 (msb) first and bcnt0 (lsb) second. 7.3.5 command acceptance the wts701 processes commands and data as they ar e sent to the device. under certain conditions the device will not be ready to accept a new command or data. if the device has not finished processing the previous command, the icmd bit of the status register will be set. if this bit is set, it implies that device is not in a position to accept the command being sent and that it will be ignored. the host should monitor this bit when a command is s ent and, if it is detected, the spi transaction should be terminated at the end of the command wo rd. the host can then resend the command until the command is accepted. 7.3.6 data acceptance the wts701 has an eight byte fifo to buffer data from the spi port to the internal processor. during a conversion, data is read from this fifo into an internal ram data buffer. if spi transmission is too fast for the wts701 to keep up with, the r/ b line will be asserted (low) to pause data transfer. alternatively, the status register c an be monitored for the state of the r/ b signal. 7.4 c ommands o verview control of the wts701 is implemented through a 16-bit command word. the command word is always the first word to follow the falling edge on the ss signal. the command word consists of the command byte followed by the command data byte . many commands do not require a command data byte, although one must be sent. for commands that have no data, the command data byte is a ?don?t care?. commands fall into five categories. commands that control an operational synthesis function of the text-to-speech processing, commands that modif y internal configuration registers, commands that change system state, commands that read inter nal status registers, and customization commands.
wts701 - 24 - status commands table 5. status opcodes. the wts701 has three read-only registers accessed by the opcodes, which are shown to the right. ? the read status register returns the device?s operational status and the numbers of bytes that have been converted. ? the read interrupt register returns the same status data and clears any of the interrupt status bits that are set. ? the version register returns the hardware and firmware version of the chip. system commands table 6. system opcodes. the wts701 responds to various system commands that change the state of the system, namely: ? the power up command wakes up the device from power down mode. ? the power down command requests that the device enter the power down mode. ? the reset command resets the device (see subsection 7.4.4 ). ? the idle command puts wts701 processor in idle mode opcode mnemonic function 0x04 rdst read status register 0x06 rint read interrupt register 0x12 rver device version opcode mnemonic function 0x02 pwup power up 0x40 pwdn power down 0x10 rst reset 0x57 idle go idle
wts701 publication release date: may 2003 - 25 - revision 3.09 synthesis commands table 7. synthesis opcodes. the synthesis commands affect the text-to-speech synthesis. they are detailed in the table to the right. the basic commands are: ? start a conversion ? pause the conversion ? resume the conversion ? stop the conversion ? finish conversion at the end of the current word. ? finish the conversion at the end of the buffer ? volume up/down ? speed up/down the text-to- speech conversion configuration commands table 8. configuration opcodes. the wts701 has several configur- ation registers. the commands are: ? the com configuration register governs the behavior of how the chip uses the int and r/ b hardware lines to communicate with the host ? the codec register con- figures the mode of the digital audio output ? the audio register sets parameters of the analog audio path ? the volume register sets the volume level of output ? the speed register sets the speed level of output speech ? the clc register sets the master clock frequency of the device ? the sptc command sets speech pitch opcode mnemonic function 0x81 conv start converting 0x49 paus pause conversion 0x4a res resume conversion 0x4b st stop conversion 0x4d finw finish word 0x4c fin finish buffer 0x53 vlup volume up 0x54 vldn volume down 0x55 spup speed up conversion 0x56 spdn slow down conversion opcode mnemonic function 0xc0 rreg read configuration register 0x4e scom com configuration register 0x4f scod codec configuration register 0x50 saud audio configuration register 0x51 svol vol configuration register 0x52 sspd speed configuration register 0x14 sclc clc (clock) configuration register 0x77 sptc set speech pitch
wts701 - 26 - customization commands table 9. customization opcodes. the wts701 has the ability for the user to customize the way in which it responds to certain text strings. this is done by way of an abbreviation table. the customization opcodes allow the user to interrogate and modify the abbreviation table. 7.4.1 command description the following section list all the standard commands that can be executed on the wts701. pwdn go to power down mode this command puts the wts701 processor in powe r-down mode. this is a single word command therefore no data is required for this command. the power down command places the wts701 device into its lowest power consumption mode. in power down mode, the device will only respond to a power up command (pwup) and read status (rdst) command. as soon as power down sequence has ended, the rdy flag in the status word is cleared. pwdn class 1 type i host controller 0x40 0x00 byte sequence: wts701 status byte 0 status byte 1 description: put the wts701 processor in power-down mode. pwup power up this command wakes up the wts701 processor to idle state. the result of this command is that the wts701 starts the power up sequence, which leads to bringing up internal supplies, resetting the processor, all configuration registers are initialized to their default values and entering idle state. as soon as power up sequence has ended, the rdy flag in the status word is asserted. the sclc command must be sent before pwup. opcode mnemonic function 0xc8 abbr_num get number of abbrev. entries 0xc9 abbr_rd read abbreviation table 0xc7 abbr_mem get number of free bytes. 0xaf abbr_add add abbrev. entry 0x83 abbr_del delete abbrev. entry 0x0c enter_rrsm swap memory
wts701 publication release date: may 2003 - 27 - revision 3.09 pwup class 0 type i host controller 0x02 0x00 byte sequence: wts701 status byte 0 status byte 1 description: wake up the wts701 processor to idle state. conv convert the convert command starts the text to speech c onversion process. the convert command is followed by ascii text data. the device has a buffer of 256 bytes. when this buffer is full, the chip pulls the r/ b line low and sets the bful bit in the status word indicating that the wts701 buffer manager is in the buffer full condition. the wts701 remains in the buffer full condition until the input buffer has been emptied of half the buffer space (128 bytes). when the buffer is full, the host may do one of three things: 1. the host may end the command at that point, then poll the bful bit of the spi status register until it is clear, and then send new conv commands with the additional ascii text data. 2. the host may also continue the command (keep ss low) and wait for the r/ b pin to go high. as each word is processed by the wts701, space will become free in the buffer and the r/ b pin will go high until it is full again. 3. the device may also be configured such that it will generate an interrupt to the host when the buffer threshold (set by rcom command) has been crossed. (see tables 3 and 4 ) this allows the host to fill the buffer then wait for the interrupt to send the additional data. during conversion, the convert count register is updated as each word has been spoken. this register is cleared to zero at power up, and at the beginning of a new conversion process after one has been terminated. a convert command is terminated in several ways: ? send a finish command (fin) indicating that the host has finished sending data. in this case, the device finishes converting the text buffe r, then stops and enters a wait state. ? the conversion process will also stop when the eot (^d, ascii 0x1a, unicode/big5 0x00 0x1a) character is part of the input text. when t he device detects the eot character, it will continue the conversion process until the buffer is emptied and the final word spoken. then it will stop and enter the wait state. ? the finish word command (finw) will cause the wts701 device to finish the word currently being spoken, then flush the buffers and enter the wait state.
wts701 - 28 - ? the stop command (st) will cause the wts701 to immediately stop converting, flush the buffer and enter the wait state. once the wait state has been entered the device will clear the convert (conv) bit from the status register and, if enabled, generate an icvt interrup t. at this stage the codec and analog path are still active. to release the codec bus, or power down the analog path, an idle command should be sent to the device. if a convert command is te rminated using any of the methods described in this section, another convert command cannot be sent unt il the previous conversion is completed. the cnvt bit must be polled to determine that convers ion is completed before a new conversion can be started. conv class 2 type iii host controller 0x81 0x00 data0 ? datan byte sequence: wts701 stadus byte 0 status byte 1 status byte 0 ? status byte n%2 description: start or continue a conversion process. data sent is text data for conversion. paus p ause this command causes a pause of the conversion pr ocess. there is no data associated with this command. the pause condition is terminated by the res (resume) command paus class 1 type i host controller 0x49 0x00 byte sequence: wts701 status byte 0 status byte 1 description: this command pauses the conversion process. res r esume this command causes the conversion to resume if it was paused. there is no data associated with this command res class 1 type i host controller 0x4a 0x00 byte sequence: wts701 status byte 0 status byte 1 description: this command resumes conversion after pause.
wts701 publication release date: may 2003 - 29 - revision 3.09 st s top this command immediately stops conversion wi thout finishing buffer, and clears the buffer. st class 1 type i host controller 0x4b 0x00 byte sequence: wts701 status byte 0 status byte 1 description: stop conversion. finw f inish w ord this command directs the wts701 to finish text conversion at the end of the current word. finw class 1 type i host controller 0x4d 0x00 byte sequence: wts701 status byte 0 status byte 1 description: this indicates that convers ion is to end with the processing of the current word. fin f inish this command indicates that no further conversion data is to follow and to stop conversion after processing the current buffer contents. fin class 1 type i host controller 0x4c 0x00 byte sequence: wts701 status byte 0 status byte 1 description: finish conversion after processing the current buffer.
wts701 - 30 - idle i dle this command is executed after the receipt of an end-of-conversion interrupt (icnv) has occurred. the idle command will deactivate all audio outputs and bring the device to the idle state. idle class 1 type i host controller 0x57 0x00 byte sequence: wts701 status byte 0 status byte 1 description: put wts701 in idle state. rdst r ead s tatus the read status command reads the status word of the device. if two dummy data bytes are also sent, the contents of the byte count registe r are also returned. refer to subsections 7.3.2 and 7.3.4 for more information regarding the status register and bcnt register. rdst class 0 type ii host controller 0x04 0x00 0x00 0x00 byte sequence: wts701 status byte 0 status byte 1 bcnt 1 bcnt0 description: read status word of the device. rver r ead v ersion the read version command reads the wts701 version information. the software version information is only valid when the device is powered up. rver class 0 type ii host controller 0x12 0x00 0x00 0x00 byte sequence: wts701 status byte 0 status byte 1 hw ver sw ver description: read wts701 software and hardware versions.
wts701 publication release date: may 2003 - 31 - revision 3.09 rint r ead i nterrupt the read interrupt command reads the status word of the device, it also clea rs the status interrupt request flags at the end of the transaction. as a re sult of this command, all interrupt bits are cleared and int pin is released. refer to subsections 7.3.2 and 7.3.4 for more information regarding the status register and bcnt register. rint class 0 type ii host controller 0x06 0x00 0x00 0x00 byte sequence: wts701 status byte 0 status byte 1 bcnt1 bcnt0 description: read status word and c lear the status interrupt bits. rreg r ead c onfiguration r egister the read configuration register command reads t he configuration register specified in the command data byte. the code 0xnn is the register number and it is described in table 10 ? configuration registers, subsection 7.4.2 . rreg class 3 type iv host controller 0xc0 0xnn 0x00 0x00 byte sequence: wts701 status byte 0 status byte 1 xx reg description: read configuration register 0xnn. note: xx = don?t care. scom s et com r egister set the com (interrupt communication) configurat ion register to value 0xnn. refer to subsection 7.4.3 describing all configuration registers and the com register in particular. the default value of this register after powe r-up or reset is 0x00. refer to subsection 7.4.3 - configuration registers, which describes all register bits. scom class 1 type i host controller 0x4e 0xnn byte sequence: wts701 status byte 0 status byte 1 description: set the com (interrupt communication) configuration register to value 0xnn.
wts701 - 32 - scod s et cod r egister set the cod (codec control) c onfiguration register to value 0xnn. the default value of this register after powe r-up or reset is 0x01. refer to subsection 7.4.3 - configuration registers, which describes all register bits. scod class 1 type i host controller 0x4f 0xnn byte sequence: wts701 status byte 0 status byte 1 description: set the cod (codec cont rol) configuration register to value 0xnn. saud s et aud r egister set the aud (analog audio) configuration register to value 0xnn. the default value of this register after powe r-up or reset is 0x43. refer to subsection 7.4.3 - configuration registers, which describes all register bits. saud class 1 type i host controller 0x50 0xnn byte sequence: wts701 status byte 0 status byte 1 description: set the aud (analog audio) configuration register to value 0xnn. svol s et vol r egister set the vol (volume) configuration register to value 0xnn. the default value of this register after powe r-up or reset is 0x07. refer to subsection 7.4.3 - configuration registers, which describes all register bits. svol class 1 type i host controller 0x51 0xnn byte sequence: wts701 status byte 0 status byte 1 description: set the vol (volume) c onfiguration register to value 0xnn.
wts701 publication release date: may 2003 - 33 - revision 3.09 sspd s et spd r egister set the spd (speech rate/speed) c onfiguration register to value 0xnn. the default value of this register after powe r-up or reset is 0x02. refer to subsection 7.4.3 - configuration registers, which describe all register bits. sspd class 1 type i host controller 0x52 0xnn byte sequence: wts701 status byte 0 status byte 1 description: set the spd (speech ra te/speed) configuration register to value 0xnn. sclc s et clc r egister set the clock configuration register (clc) to value 0xnn. the value of this register must be set before power-up or reset command to 0x00. refer to subsection 7.4.3 - configuration registers, which describes all register bits. sclc class 0 type i host controller 0x14 0xnn byte sequence: wts701 status byte 0 status byte 1 description: set the clock configuration register (clc) to value 0xnn. sptc s et s peech p itch set the speech pitch to value 0xnn. the valid pitch values are between 0x00 and 0x06 while the default pitch value is 0x05, and these values can be used to control the speech output pitch. the command can be executed only when t he wts701 is in idle state. sptc class 1 type i host controller 0x77 0xnn byte sequence: wts701 status byte 0 status byte 1 description: set the speech pitch parameter to value 0xnn.
wts701 - 34 - vlup v olume -u p c ommand increment the volume (vol) register. has no effect if already at maximum volume. the default value of this register after powe r-up or reset is 0x07. refer to subsection 7.4.3 - configuration registers, which describes all register bits. vlup class 1 type i host controller 0x53 0x00 byte sequence: wts701 status byte 0 status byte 1 description: increment the volume (vol) register. vldn v olume d own c ommand decrement the volume (vol) register. this has no e ffect if already at minim um volume. the default value of this register after power-up or reset is 0x07. refer to subsection 7.4.3 - configuration registers, which describes all register bits. vldn class 1 type i host controller 0x54 0x00 byte sequence: wts701 status byte 0 status byte 1 description: decrement the volume (vol) register. spup s peed u p c ommand increase speaking rate (spd register). this has no effect if already at maximum speaking rate. the default value of this register after power-u p or reset is 0x02. refer to subsection 7.4.3 - configuration registers, which describes all register bits. spup class 1 type i host controller 0x55 0x00 byte sequence: wts701 status byte 0 status byte 1 description: increase speaking rate (spd register).
wts701 publication release date: may 2003 - 35 - revision 3.09 spdn s peed d own c ommand decrease speaking rate (spd register). has no e ffect if already at minimum speaking rate. the default value of this register after power-u p or reset is 0x02. refer to subsection 7.4.3 - configuration registers, which describes all register bits. spdn class 1 type i host controller 0x56 0x00 byte sequence: wts701 status byte 0 status byte 1 description: decrease speaking rate (spd register). rst r eset c ommand sending this command has the same affect as a power-on reset, the wts701 enters the power down state. rst class 0 type i host controller 0x10 0x00 byte sequence: wts701 status byte 0 status byte 1 description: reset the wts701 device. abbr_add a dd a bbreviation add an entry to the abbreviation table. abbr_add class 2 type iii host controller 0xaf 0x00 data0 ? datan byte sequence: wts701 status byte 0 status byte 1 status byte 0 ? status byte n%2 description: add an entry to the abbreviation table..
wts701 - 36 - abbr_mem r eturn a bbreviation m emory the abbr_mem command will return the number of bytes available in the abbreviation table in mem_hi and mem_low. abbr_mem class 3 type iv host controller 0xc7 0x00 0x00 0x00 byte sequence: wts701 status byte 0 status byte 1 mem_hi mem_low description: return the number of bytes available in the abbreviation table. abbr_num r eturn n umber of a bbreviation e ntries the abbr_num command will return the number of abbreviation entries in the abbreviation table in num_hi and num_low. abbr_num class 3 type iv host controller 0xc8 0x00 0x00 0x00 byte sequence: wts701 status byte 0 status byte 1 num_hi num_low description: return the number of abbr eviation entries in the abbreviation table. abbr_rd r ead a bbreviation t able the abbr_rd command will return the abbreviation t able. this command must read 2048 bytes after receiving the status register. abbr_rd class 3 type iv host controller 0xc9 0x00 0x00 ?.. 0x00 byte sequence: wts701 status byte 0 status byte 1 abbr0 ?.. abrrn description: return the 2048 bytes of abbreviations.
wts701 publication release date: may 2003 - 37 - revision 3.09 abbr_del d elete a bbreviation e ntry this command deletes abbreviation entry from abbreviation table. abbr_del class 2 type i host controller 0x83 0x00 data0 ? datan byte sequence: wts701 status byte 0 status byte 1 status byte 0 ? status byte n%2 description: delete an entry fr om the abbreviation table. enter_rrsm s wap m emory this command is used in programming mode, and caus es the xdata and code store memory to swap spaces. please refer to subsection 7.8 for more information about customizing abbreviations. enter_rrsm class 0 type i host controller 0x0c 0x00 byte sequence: wts701 status byte 0 status byte 1 description: swap memory between xdata and code store. 7.4.2 illegal commands all commands described in section 7.4.1 are the only legal commands that should be sent to the wts701 device, unless stated otherwise. other comm ands should not be sent to the device, as the device behavior cannot be predicted. specific illegal commands are those in which the 2 most significant bits of the command byte are zeros and are not defined in this document as commands allowed to be sent to the wts701. 7.4.3 configuration registers the configuration registers are accessed by sending the appropriate configuration command followed by a single byte of data to load the register. the def inition of the contents of the various registers is given below. the default value for each of these registe rs after power up or reset is also described in table 10 .
wts701 - 38 - table 10. configuration registers. msb lsb register reg. # default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 com 0x4e 0x00 icnt ibuf icnv x x x buf1 buf0 cod 0x4f 0x01 x x x x x md2 md1 md0 aud 0x50 0x43 aopu sppu spg fdth x x aig1 aig0 vol 0x51 0x07 x x x x x vl2 vl1 vl0 clc 0x14 none x x x clc4 clc3 clc2 clc1 clc0 spd 0x52 0x02 x x x x x spd2 spd1 spd0 x = reserved. the bits of each register are described below: com register icnt if set to a ?1?, the device will generate an interrupt when the count register has been updated. this occurs after each word has been spoken. ibuf if set to ?1?, the device will generate an interrupt when the buffer level crosses the threshold set by the buf bits. (see table 3 , status bytes). icnv if set to ?1?, the device will generate an interrupt when the end of a conversion is reached. buf1..0 if ibuf is set, buf1..0 determines the buffer level at which the interrupt will be generated. 00b ? input buffer empty. 01b ? input buffer <10% full. 10b ? input buffer <50% full. 11b ? input buffer <75% full.
wts701 publication release date: may 2003 - 39 - revision 3.09 cod register md2 codec enable, possible modes are: 0b: codec disabled. 1b: codec enabled during conversion. md1 codec precision, possible modes are: 0b: 13 bit linear pcm output 1b: 16 bit linear pcm output. md0 codec output format, possible modes are: 0b: unsigned pcm output 1b: 2?s complement pcm output. aud register aopu 1b: power up the analog output buffer. sppu 1b: power up the analog speaker driver. spg speaker driver gain selection. 0b: 8 ? speaker. a v = 1.32 1b: 100 ? speaker. a v = 1.6 fdth 1b: enable feed-through path from auxin to auxout. aig1..0 auxin gain setting 00b ? 0db 01b ? 3db 10b ? 6db 11b ? 9db
wts701 - 40 - vol register vl2..0 volume level of output. 000 ? 0db 001 ? -4db 010 ? -8db 011 ? -12db 100 ? -16db 101 ? -20db 110 ? -24db 111 ? -28db each step gives a 4db attenuation of output. clc register clc4..0 configure the device for differ ent master clock frequencies. 0x00 24.576 mhz 0x10 16.384 mhz 0x08 32.768 mhz (the only clock frequency currently recommended for operation is 24.576mhz.) spd register spd2..0 configure the speech speed register. 0x04 is the fastest speed and 0x00 is the slowest.
wts701 publication release date: may 2003 - 41 - revision 3.09 7.4.4 system operation the wts701 is a single chip solution for text-to-s peech synthesis. the text-to-speech operation is accomplished by a process of screening the incom ing text to normalize common abbreviations and numbers into a spoken form. the normalized text is then analyzed for phonetic interpretation and this phonetic translation is mapped into samples to be play ed out of the analog storage array. this output signal is then smoothed by a low-pass filter and is available as an analog signal, or can be passed through the codec for digital audio output. the wts701 processor state machine the wts701 functions as a state machine and changes states either in response to a command sent by the host controller, after execution of command is completed, or as a result of an internal event. the wts701 states are described below in reference to figure 10 . power down idle wait convert reset figure 10. wts701 processor states vcc a pp lied hard reset idle convert convert soft reset pwdn pwup pwdn, soft reset hard reset soft reset, pwdn stop finish finish word conversion finished
wts701 - 42 - reset the wts701 processor is initialized to the reset state when vcc is first applied to the part. after a reset condition the device enters the powe r down state. all configuration registers are initialized to their default values after issuing the pwup command. once the wts701 is active and a hardware reset is applied on the reset pin, the wts701 will be in idle state, and all configuration registers will return to their default values. power down in this state, the power consumption of the wt s701 is minimal. all analog outputs are tristate, the crystal interface is deactivated and the microcont roller is stopped. the only commands valid in the power down mode are pwup, sclc and rdst. all c onfiguration registers will return to their default values after issuing the pwup command. idle the idle state is first entered with the pwup comm and. in this state, the micro-controller is running and the device is ready to respond to further comm ands. from the idle state, the device can go to the active convert state or the power down state. convert this state is initiated by the co nv command. the text located in t he internal buffer is converted into speech and played back to the analog or digital interface according to the state of the configuration registers. once the active conversion has finished, the device ente rs the wait state. wait once a conversion has finished, the device enters the wait state. in this state, audio outputs are still active. to deactivate, audio outputs and return to the idle state an idle command is issued.
wts701 publication release date: may 2003 - 43 - revision 3.09 7.4.5 initialization and configuration configuration after power-on or a reset command (rst) the wts701 processor can be configured for operation. this involves initializing the internal configurat ion registers for the users requirements. table 11. initialization commnad sequence state command description power down -------- state after power-on or rst command. sclc set clock configuration. pwup power up device. idle scom set up communication register to enable interrupts. scod set up codec configuration (if used). saud set up audio control register. svol set the initial volume level. sspd set the initial speech output speed level. sptc set the initial speech pitch level. 7.4.6 converting text after configuration, the wts701 is ready for text-t o-speech conversion. because of the real-time nature of speech, some form of flow cont rol is necessary to inform the host system: 1. when the device is ready for more text data 2. when the device has finished converting text 3. when the device can release the audio interface the convert state is entered by sending a co nv command along with some textual data. the wts701 has an internal 256-byte buffer to accept text data. the r/ b signal (both the hardware line and the status bit) will become active (low): 1. when the internal buffer is full 2. if the host sends data at a rate too fast fo r the wts701 to process it to the internal buffer when r/ b becomes active the user may: 1. wait for the r/ b pin to return to the (high) ready state 2. terminate the spi transaction until a later time and resend the data
wts701 - 44 - the user has the choice of enabling interrupts to signal the host when there is free space in the internal buffer. when all text data has been s ent, the user must indicate this by: 1. sending a fin (finish) command 2. sending an eot (ascii 0x1a) character as the last byte of a conv command (mandarin unicode /big5 0x00 0x1a) when conversion has been terminated using either of these commands, another conv command cannot be sent until conversion is complet ed and the chip enters the wait state. notes 1. buffer length limit: the max. character length of a white-spac e-bounded string is 53. the exceeding characters will be truncated. 2. undefined characters: all the undefined characters will be deleted (prior to the word pronounciation process). the defined characters range from ?0x00? to 0x7a ? excluding ?0x22?, ?0x3c ?, ?0x3e? and ?0x60?. once the wts701 has synthesized the contents of the text buffer, it will enter the wait state. in this state the audio interface is still active. to disable t he audio interface and return to the idle state an idle command is sent. the wait state can be detected either through polling of the cnvt bit or enabling of the icnv interrupt. an example of the flow for a conversion is shown in figure 11 . the flow here assumes that the com register is set su ch that the wts701 generates an ibuf interrupt at the 75 percent buffer level (64 free bytes) and that the icnv interrupt is enabled.
wts701 publication release date: may 2003 - 45 - revision 3.09 idle send conv command fill serial buffer with text data wait for ibuf interrupt write a new batch of text data to buffer ( < 192 bytes otherwise buffer may overflow) sent all data? send fin command yes wait for icnv interrupt or cnvt cleared send idle command no figure 11. flow diagram for convert operation.
wts701 - 46 - controlling text conversion the wts701 offers several features to contr ol text conversion. the paus (pause) and res (resume) commands allow the host to pause and then continue speech output. the finw command allows the host to end a conversion after the next w hole word is spoken. the st (stop) command will terminate a conversion immediately ? even mid-word. to allow more advanced control, the wts701 allows the host to interrogate the byte count registe r, which keeps track of the position in the input stream that is currently being spoken. if the hos t wishes to repeat a spoken word, it should: 1. read the byte count register 2. send a finw or st command 3. wait for icnv 4. send a new conv command resending the data starting at the desired number of bytes, according to the repeated spoken words, prior to the count returned in the byte count in a similar way a skip function could be implemented to skip ahead words or sentences. 7.5 spi i nterface the spi interface consists of the 4-wire bus ss , sclk, mosi and miso. in addition, flow control protocols are implemented via the r/ b signal and/or the wts701 status register transmitted via mosi. the wts701 processor also has the option to co mmunicate with the host via interrupt services requested by the interrupt request line. the timing and behavior of these signals is dependent upon the command class being executed, i.e., commands wi th or without associated data. additionally the use of the r/ b hardware control line is not compulsory; rather the host can monitor the r/ b bit of the status register to determine when data has been accepted. the status register also contains the icmd bit. this bit is set to indicate an spi transaction has been ignored, indicating that the wts701 processor is unable to service a new command. asynchronous (class 0) commands are always accepted. for more information, refer to subsection 7.3.1 which describes the command classes. 7.5.1 spi transactions spi transactions with the wts701 are broken down into four classes and four basic types: type i - single word transactions single word transactions are class 0 or class 1 co mmands that have no data to transmit or transmit all required data in the command data byte. r/ b will never become active for these commands. icmd could be active for a class 1 command if the wts701 is still interpreting the previous command.
wts701 publication release date: may 2003 - 47 - revision 3.09 0 1 2 3 4 5 6 70 1 2 3 4 5 6 7 command byte command data byte 0 0 00 0 0 0 icnt ibufi icnv cod bful bemp cnvt rdy r/b icmd sclk mosi miso ssb iabb figure 12. type i spi transaction. type ii ? two word transactions that receive data type ii transactions are four byte transactions that read out the byte count register. as these commands are all class0, icmd will never be active and r/ b will never occur. command byte command data byte data byte 0 (even) data byte 1 (odd) icnt ibufi icnv cod bful bemp cnvt rdy r/b iabb icmd sclk mosi miso ssb bcnt0 bcnt1 0 1 2 3 4 5 6 70 1 2 3 4 5 6 7 0 0 00 0 0 0 1 2 3 4 5 68 9 a b c d e f 7 0 figure 13. type ii spi transaction. type iii ? transactions that send data type iii transactions send data to the wts701. if t he data rate exceeds the ability of the wts701 to read data from the input fifo or if t he internal data queue becomes full then the r/ b line will handshake a pause in the spi trans action. the host can either: ? wait for r/ b to return high then continue sending data ? terminate the transaction and try sending data later
wts701 - 48 - 0 1 2 3 4 5 6 70 1 2 3 4 5 6 7 command byte command data byte 0 0 00 0 0 icnt ibufi icnv cod bful bemp cnvt rdy r/b iabb icmd sclk mosi miso ssb sclk mosi miso ssb 0 1 2 3 4 5 6 70 1 2 3 4 5 6 7 0 0 00 0 0 1 2 3 4 5 6 70 1 2 3 4 5 6 7 data n+2 (even) data n+3 (odd) 0 0 00 0 0 0 data n (even) data n+1 (odd) r/b low with spi end r/b 0 icnt ibufi icnv cod bful bemp cnvt rdy r/b iabb icmd icnt ibufi icnv cod bful bemp cnvt rdy r/b iabb icmd figure 14. type iii spi transaction. type iv ? transactions reading data type iv transactions read data from the wts701. because of the latency required for the wts701 to place data in the output register, r/ b must be monitored. 0 1 2 3 4 5 6 70 1 2 3 4 5 6 7 command byte command data byte 0 0 00 0 0 data byte 0 (even) data byte 1 (odd) 0 1 2 3 4 5 60 1 2 3 4 5 6 7 7 0 icnt ibufi icnv cod bful bemp cnvt rdy r/b iabb icmd sclk mosi miso ssb r/b figure 15. type iv spi transaction.
wts701 publication release date: may 2003 - 49 - revision 3.09 7.6 codec i nterface the wts701 processor supports analog and digital t elephony in various configurations. the wts701 can be used in digital environments, along with a dsp that controls a codec. therefore, the wts701 is configured to operate in slave mode, wher e the control signals are provided by an external source, which is usually the dsp. it supports a variety of single channel codecs, examples of which are listed in table 12 . the codec interface is designed to send data in shor t frame format as well as long frame format. the channel width is 13 or 16 bits linear, the precision of the output is 10 bits. the operation mode of the codec is configured by the cod configurat ion register and scod command. see subsection 7.4.3 for details. ? the codec can be configured to transmit data in the unsigned or 2?s complement mode (see table 13 for details). ? the codec responds to both the long and short sync format (see figure 16 and figure 17 ). ? the codec can be configured to tristate the vdx line after 13 or 16 bits. table 12. supported codec examples. manufacturer codec device name characteristics operating voltage conversion type data format oki ml7041 single codec 3 v 14-bit linear 2s complement oki msm7716 single codec 3 v 14-bit linear 2s complement oki msm7732-011 single codec 3 v 14-bit linear 2s complement motorola mc145483 single codec 3 v 13-bit linear 2?s complement lucent t8538b quad codec 3.3 v 16-bit linear 2?s complement
wts701 - 50 - table 13. codec transmission modes. signed mode (2?s complement) unsigned mode level sign bit (msb) 13 bit mode 16 bit mode 13 bit mode 16 bit mode +ve full scale 0 1111 1111 1000 1111 1111 1000 0000 1 1111 1111 1000 1111 1111 1100 0000 +1 lsb 0 0000 0000 1000 0000 0000 1000 0000 1 0000 0000 1000 1000 0000 0100 0000 zero (ground) 0 0000 0000 0000 0000 0000 0000 0000 1 0000 0000 0000 1000 0000 0000 0000 -1 lsb 1 1111 1111 1000 1111 1111 1000 0000 0 1111 1111 1000 0111 1111 1100 0000 -ve full scale 1 0000 0000 0000 0000 0000 0000 0000 0 0000 0000 0000 0000 0000 0000 0000 13 12 11 10 9 8 7 6 5 4 0 0 vdx vclk vfs msb lsb 0 figure 16. codec protocol, 13 bit, short frame sync.
wts701 publication release date: may 2003 - 51 - revision 3.09 13 12 11 10 9 8 7 6 5 4 0 0 vdx vclk vfs msb lsb 0 figure 17. codec protocol, 13 bit, long frame sync. 4000 vdx vclk vfs 0 msb lsb 3 zeros 10 9 8 7 6 13 12 11 50 0 figure 18. codec protocol, 16 bit, short frame sync.
wts701 - 52 - 4000 vdx vclk 0 msb lsb 3 zeros 10 9 8 7 6 13 12 11 50 0 vfs figure 19. codec protocol, 16 bit, long frame sync. 7.7 c ontrol c haracters the wts701 allows receiving control characters em bedded in the text sent in the convert command to better emphasize word or alter meaning of sent ence. the control characters supported are for phonetic alphabet playback, speed, volume modif ication and case sensitivity behavior. 7.7.1 phonetic alphabet playback the wts701 uses an intermediate phonetic translat ion represented as an alphabet that represents phonemes and stress for each input word. this feature allows the text sent to the wts701 to consist of a combination of ascii characters as well as phonetic alphabet. this capability offers the flexibility to send words already processed for phonetic representation, achieving the desired pronunciation. phonetic strings can be sent directly to the wts701. this can be done by embedding phoneme strings in the text stream for conversion. to embed a phoneme string, the string must be preceded by a control-p (^p, ascii 0x 10) character and terminated by a space character. for example: ?the quick ^pbr1wn fox.? the following table lists the phoneme symbols a cceptable by the wts701e (english software version). as the acceptable phoneme symbols ar e language dependent, please refer to the specific language user?s guide for details regarding c haracters accepted and other development considerations.
wts701 publication release date: may 2003 - 53 - revision 3.09 table 14. acceptable phoneme symbols. vowels consonants phoneme hex value example phoneme hex value example i 0x69 b ea t p 0x70 pet i 0x49 b i t t 0x74 t en e 0x65 b a it k 0x6b k it e 0x45 b e t b 0x62 b et @ 0x40 b a t d 0x64 d ebt u 0x75 b oo t g 0x67 g et u 0x55 b oo k h 0x68 h at o 0x6f b oa t f 0x66 f at c 0x63 b ou ght t 0x54 th ing a 0x61 b o b d 0x44 th at a 0x41 b u t s 0x73 s at r 0x52 b urr s 0x53 sh ut o 0x4f b oy v 0x76 v at y 0x59 b uy z 0x7a z oo w 0x57 d ow n z 0x5a a z ure x 0x78 a bout y 0x79 y ou x 0x58 ros e s w 0x77 w it r 0x72 r ent l 0x6c l et m 0x6d m et n 0x6e n et g 0x47 si ng c 0x43 ch ur ch j 0x4a j u dge p 0x50 bu tt er* q 0x51 wri tt en* note that each phoneme is represented by exactl y one character and each vowel is preceded by a stress symbol . * female english only.
wts701 - 54 - numbers 1 and 0 represent stress: each word has a single 1 stress, representing the main stress of the word; all other syllables have 0 stress. examples: input phonetic translation hi. h1y (phoneme /h/, followed by a 1-stress vowel phoneme y) test t1est testing t1est0ig special characters in text input string these characters inserted into the ascii text are used to modify the behavior for special circumstances. 0x10 ^p this control flag indicates a phoneme string follows immediately (e.g. ?^ppr0ez0intles0in?). 0x11 ^q pauses with variant length can be added wi thin a sentence by using the ?^qx? flag. ?x? is an integer which indicates the pause duration (?x? is 0.1 sec per unit). for instance, ?^q10? will add in a 1-second pause. it is important to remember that all the text f ollowing these special characters will be subjected to the same special conditions. if a ^v+ command precedes a word then all the following words will be spoken louder. if a single word is to be emphasized then the ^v+ must be ahead of the word and a ^v- must follow. 7.7.2 speed change the rate of speech can be changed by sending an spi command to modify the speed or by adding a control character to cont rol the speed in real-time. 0x13 ^s speed change flag. a space character is required after the control characters before the input text string. ? ^s+: increase speed by 1 (e.g. ?^s+ hello world?). ? ^s-: decrease speed by 1. ? ^sx: set the speed to x. x starts from 0 to 4 (e.g. ?^s1 hello world?). any number that is greater than 4 will be set to 4. it?s the user?s responsibility to verify the wt s701 speed setting before sending a control character and/or spi command that modify speed.
wts701 publication release date: may 2003 - 55 - revision 3.09 7.7.3 volume change the speech volume can be changed by sending spi command to modify the speed or by adding control character to contr ol the volume in real-time. 0x16 ^v volume change flag. a space characte r is required after the control characters before the input text string. ? ^v+: increase volume by 1 (e.g. ?^v+ hello world?). ? ^v-: decrease volume by 1. ? ^vx: set the volume to x. x starts from 0 to 7 (e.g. ?^v1 hello world?). any number that is greater than 7 will be set to 0. it?s the user?s responsibility to verify the wts 701 volume setting before sending a control character and/or spi command that modify volume. 7.7.4 case sensitivity the way upper/lower case is handled can be changed by adding a control character in the text sent to control the case sensitivity behavior in real-time. 0x15 ^u all-uppercase word (all caps) control flag. this flag controls interpretation of strings with all uppercase letters. a space character is r equired after the control characters before the acutual input text string. ? ^u0: this is the default setting. some all-uppercase words (all caps) are spelled out, but others are treated as ordinary words, abbreviat ions, roman numerals, ect. (e.g. ?^u0 ibm equals ?i b m?). ? ^u1: avoid spelling out all-uppercase words. any all-uppercase word in the input string will not be spelled out unless the system determines t hat the word is not pronounceable. in this mode, there is no abbreviation support (e.g. ?^u1 nokia? equals ?nokia?). ? ^u2: spell out all words, regardless of case . all words in the input sting are spelled out in this mode. there is no abbreviation support in this mode (e.g. ?^u2 nokia? equals ?n o k i a?). ^u3: force the all-capital words/strings to be spelled out regardless of string length. for instance, ?^u3 hello? will be pronounc ed as ?h?, ?e?, ?l?, ?l?, ?o?. 7.7.5. pause control pause control flage: ?^qx?: pauses with var iant length can be added within a sentence by using the ?^qx? flag. ?x? is an integer which indicats the pause duration (?x? is 0.1 sec per unit). for instance, ?^q10? will add in a 1-second pause.
wts701 - 56 - 7.8 c ustomizing a bbreviations the wts701 has support for entering and using custom abbreviations in addition to the general abbreviation table supported internally by the wts701. there are 2k by tes of flash memory reserved for this purpose. after the wts701 internal softwar e has been initially programmed, this entire area is free and available for custom abbreviations. the commands associated with custom abbreviations are: command command byte command data byte abbr_add 0xaf 0x00 + abbreviation data. adds a new abbreviation to the abbreviation table in the wts701 see next page for the format of the abbreviation data. abbr_del 0x83 0x00+ abbreviation data. deletes an existing abbreviation from the abbreviation table in the wts701. see next page for the format of the abbreviation data. abbr_num 0xc8 0x00 + 0x00 + 0x00. returns the number of abbreviation currently active in the abbreviation table of the wts701. abbr_mem 0xc7 0x00 + 0x00 + 0x00. returns the number of free bytes in the abbreviation table of the wts701. abbr_rd 0xc9 0x00 + 2048 0x00s. returns the abbreviation table contents from the wts701. see next page for the format of the abbreviation table data. enter_rrsm 0x0c 0x00 causes the xdata and code store memory to swap spaces. the wts701 begins to execute code previously stored into xdata after this command. 7.8.1 abbreviation data format the format of the abbreviation data that is s ent with the abbr_add and abbr_del commands is: xxx + ?,? + yyyy + ?;?. xxx - the abbreviation characters. ?,? ? comma. yyyy ? abbreviation text.
wts701 publication release date: may 2003 - 57 - revision 3.09 ?;? ? semi-colon. example: tts,text to speech; after this is added using the abbr_add command, when the text ?tts? is sent as part of the convert data, the wt s701 will speak ?text to speech? instead of t t s. note: when deleting an abbreviation, the abbreviation text is optional. to delete the tts example, only ?tts,;? is necessary. 7.8.2 abbreviation table format the format of the abbreviation table returned with the abbr_rd command is: abbreviation entry - marker + c ount + xxx + 0x00 + yyyy + 0x00. marker ? the marker will be either 0xfe for acti ve abbreviation or 0xfc for a deleted abbreviation. count ? the byte count for this entry including the marker, count, xxx, yyyy, and zeros. xxx ? the abbreviation characters. 0x00 ? null terminator. yyyy ? abbreviation text. 0x00 ? null terminator. the unused data are always 0xff. 7.8.3 command execution abbr_num & abbr_mem - these commands are executed by sending the command and command data, waiting for r/ b to be ready, then receiving two bytes from miso. the first byte received is the msb, and the second is lsb. abbr_rd ? this command is executed by s ending the command and command data, waiting for r/ b to be ready, then receiving 2048 char acters (the entire abbreviation table). abbr_add & abbr_del ? these commands are executed by sending the command and command data, followed by the abbreviation data formatted as described in subsection 7.8.1 . when the wts701 is ready for the next step, it will generate an iabb interrupt. after the interrupt, send the enter_rssm (0x0c + 0x00) command. after issuing the command wait for 100ms. after the timeout, the wts701 will have programmed the new abbrev iation entry and be ready to accept more commands. adding or removing an abbreviation will rese t the configuration registers to their default values.
wts701 - 58 - after abbreviation entry deletion, t he abbreviation entry is only deleted from the table and not used, however it still holds memory space. the only wa y to free all memory will be to reprogram the wts701 firmware into the device . 7.9 d evice p rogramming the wts701 is fully programmable to support diffe rent available languages or different voices that can be loaded to the device whenever the user wi shes to do so. the language or the voice module should be stored externally and transmitted to the wt s701 processor with regards to a specific protocol defined in this section. programming the wts701 consists of downloading a binary executable to the processor code memory and a digitized analog speech corpus to the non-volatile analog multi- level storage (mls). winbond will supply code as a set of ascii readable dat a files. the information will be provided to qualified customers upon request.
wts701 publication release date: may 2003 - 59 - revision 3.09 7.10 t ext -t o -s peech p rocessor c ommmands ? q uick r eference t able . status commands command description opcode hex previous state result state command parameters return value name class type command byte command data description bytes description rdst 0 ii read status 04 00 idle, convert, power down no change none - byte count rint 0 ii read interrupt 06 00 idle, convert no change none - byte count rver 0 ii read version 12 00 idle, convert no change none - hw_ver, sw_ver
wts701 - 60 - system commands command description opcode hex previous state result state command parameters return value name class type command byte command data description bytes description bytes pwup 0 i exit power down mode 02 00 power down idle none - none - pwdn 1 i go to power down mode 40 00 idle, convert wait power down none - none - rst 0 i reset 10 00 idle, convert wait, power down power down none - none -
wts701 publication release date: may 2003 - 61 - revision 3.09 synthesis commands command description opcode hex previous state result state command parameters return value name class type command byte command data description bytes description bytes conv 2 iii convert text 81 00 idle, wait convert text data n none - paus 1 i pause conversion 49 00 convert no change none - none - res 1 i resume conversion 4a 00 convert no change none - none - st 1 i stop conversion 4b 00 convert wait none - none - finw 1 i finish word 4d 00 convert wait none - none - fin 1 i finish 4c 00 convert wait none - none - vlup 1 i volume up 53 00 idle, convert wait no change none - none - vldn 1 i volume down 54 00 idle, convert wait no change none - none - spup 1 i speed up 55 00 idle, convert wait no change none - none - spdn 1 i speed down 56 00 idle, convert wait no change none - none - idle 1 i switch to idle state 57 00 wait, convert idle none - none -
wts701 - 62 - configuration commands command description opcode hex previous state result state command parameters return value name class type command byte command data description bytes description rreg 3 iv read configuration register c0 register number idle, convert no change none - registe r value, dummy byte scom 1 i set com register 4e value idle, wait no change none - none scod 1 i set cod register 4f value idle, wait no change none - none saud 1 i set aud register 50 value idle, wait no change none - none svol 1 i set vol register 51 value idle, wait no change none - none sspd 1 i set spd register 52 value idle, wait no change none - none sclc 1 i set clc register 14 value idle, wait no change none - none sptc 1 i set speech pitch 77 value idle, wait no change none - none
wts701 publication release date: may 2003 - 63 - revision 3.09 customization commands command description opcode hex previous state result state command parameters return value name class type command byte command data description bytes description abbr_ num 3 iv return number of abbreviation entries c8 00 idle no change none - num_of_entries abbr_ rd 3 iv read abbreviation table c9 00 idle no change none - abbreviation table entries abbr_ mem 3 iv return abbreviation memory c7 00 idle no change none - available_mem abbr_ add 2 iii add abbreviation af 00 idle no change abbreviation information n none abbr_ del 1 i delete abbreviation entry 83 00 idle no change abbreviation information n none enter _rrs m 0 i swap memory 0c 00 idle no change none - none
wts701 - 64 - 7.10.1 text input format the following table lists the ascii characters acc eptable by the wts701e (english software version). please refer to the specific language user?s guide for more details regarding characters accepted and other development considerations. note: unexpected behavior may occur if the input text contains characters that are not defined in this ascii table. table 15. allowable ascii characters. 0x0 0x20 space 0x40 @ 0x60 0x1 0x21 ! 0x41 a 0x61 a 0x2 0x22 0x42 b 0x62 b 0x3 0x23 # 0x43 c 0x63 c 0x4 0x24 $ 0x44 d 0x64 d 0x5 0x25 % 0x45 e 0x65 e 0x6 0x26 & 0x46 f 0x66 f 0x7 0x27 ? (apostrophe) 0x47 g 0x67 g 0x8 0x28 ( 0x48 h 0x68 h 0x9 0x29 ) 0x49 i 0x69 i 0xa 0x2a * 0x4a j 0x6a j 0xb 0x2b + 0x4b k 0x6b k 0xc 0x2c , (comma) 0x4c l 0x6c l 0xd 0x2d - (dash) 0x4d m 0x6d m 0xe 0x2e . (period) 0x4e n 0x6e n 0xf 0x2f / (slash) 0x4f o 0x6f o 0x10 ^p 0x30 0 0x50 p 0x70 p 0x11 ^q 0x31 1 0x51 q 0x71 q 0x12 0x32 2 0x52 r 0x72 r 0x13 ^s 0x33 3 0x53 s 0x73 s 0x14 0x34 4 0x54 t 0x74 t 0x15 ^u 0x35 5 0x55 u 0x75 u 0x16 ^v 0x36 6 0x56 v 0x76 v 0x17 0x37 7 0x57 w 0x77 w 0x18 0x38 8 0x58 x 0x78 x 0x19 0x39 9 0x59 y 0x79 y 0x1a eot 0x3a : (colon) 0x5a z 0x7a z 0x1b 0x3b 0x5b ] (right bracket) 0x7b 0x1c 0x3c 0x5c \ (back slash) 0x7c 0x1d 0x3d = 0x5d [ (left bracket) 0x7d 0x1e 0x3e 0x5e 0x7e 0x1f 0x3f ? 0x5f _ (under score) 0x7f
wts701 publication release date: may 2003 - 65 - revision 3.09 7.10.2. buffer length limit the max. character length of a white-space- bounded string is 53. the exceeding characters will be truncated. 7.10.3. undefined characters all the undefined characters will be deleted (prior to the word pornunciation process). the difined characters range from ?0x00? to ?0x7a ? excluding ?0x22?, ?0x3e?, and ?0x60?.
wts701 - 66 - 8. timing waveforms 8.1 spi t iming d iagram ss sclk mosi t ssh t dih t dis t sss t ssmin t sclkhigh t sclklow t df t pd miso tristate tristate figure 20. spi timing specification. ss sclk t rblow t rbh t rbd r/b bit 7 bit 0 figure 21. spi r/ b timing.
wts701 publication release date: may 2003 - 67 - revision 3.09 table 16. spi timing parameters (see figure 20 and figure21 ) symbol parameters min typ (7) max units conditions t sss ss setup time 100 ns t ssh ss hold time 100 ns t dis data in setup time 50 ns t dih data in hold time 50 ns t pd output delay 100 ns t df output delay to hiz 100 ns t ssmin ss high 200 ns t sckhi sclk high time 80 ns t scklow sclk low time 80 ns t rbd delay sclk hi to r/ b low 80 ns t rblow r/ b low time 0 ms t rbh sclk hold time from r/ b\ high 0 f o clk frequency 5000 khz
wts701 - 68 - 8.2 codec t iming d iagrams msb msb-1 lsb t sync t fsp t sx t x t dv t dhi vfs vclk vdx figure 22. codec timing ? short frame sync. msb msb-1 lsb t sync t fsp t sx t x t dv t dhi vfs vclk vdx figure 23. codec timing -- long frame sync.
wts701 publication release date: may 2003 - 69 - revision 3.09 table 17. codec timing parameters (see figure 22 and figure 23 ) symbol parameters min typ (7) max units conditions t clk bit clock frequency 128 2048 khz t sync frame sync. frequency 8 khz d c clock duty cycle 45 50 55 % t ir rise time 50 ns all digital inputs t if fall time 50 ns all digital inputs t fsp frame sync. pulse width 100 ns vfs t rs receive sync. timing 20 ns vclk to vfs t sr receive sync. timing 80 ns vfs to vclk t dv output delay time for vdx valid 10 140 ns vclk to vdx t dhi output delay time for vdx high impedance 10 140 ns vclk to vdx
wts701 - 70 - 9. absolute maximum ratings table 18. absolute maximum ratings (packaged parts) (1) condition value junction temperature 150 0 c storage temperature range -65 0 c to +150 0 c voltage applied to any pin (v ss - 0.3v) to (v cc + 0.3v) voltage applied to any pin (input cu rrent limited to +/-20 ma) (2) (v ss ? 1.0v) to (v cc + 2.2v) lead temperature (soldering ? 10 seconds) 300 0 c v cc - v ss -0.3v to +7.0v table 19. operating conditions (packaged parts). condition value commercial operating temperature range (3) 0 0 c to +70 0 c extended operating temperature (2) -20 0 c to +70 0 c industrial operating temperature (2) -40 0 c to +85 0 c supply voltage (v cc ) (4) +2.7v to +3.3v ground voltage (v ss ) (5) 0v 1 stresses above those listed may cause permanent damage to the device. exposure to the absolute maximum ratings may affect device reliability. functiona l operation is not implied at these conditions. 2 all input pins except for cs signal, which is 3v tolerant only. 3 case temperature. 4 v cc = v cca = v ccd . 5 v ss = v ssa = v ssd
wts701 publication release date: may 2003 - 71 - revision 3.09 10. electrical characteristics (v cc = 3.3v, v ss = 0v, t a = 0 to 70 c) table 20. general parameters. parameter symbol test conditions spec unit min (6) typ (7) max. input low voltage v il v cc x 0.2 v input high voltage v ih v cc x 0.8 v output low voltage v ol i ol = 10 a 0.4 v r/ b , int output low voltage v ol1 i ol = 1 ma 0.4 v output high voltage v oh i ol = -10 a v cc ? 0.4 v v cc current (operating) - convert - idle - codec - speaker i cc no load (8) no load (8) no load (8) no load (8) 50 20 20 15 ma ma ma ma v cc current (standby) i sb (8) 1 50 a input leakage current i il +/-1 a 6 all min/max limits are guaranteed by winbond via electrical testing or characterization. not all specifications are 100% tested. 7 typical values are t = 25 c and v cc = 3.0v, timing measured at 50% levels. 8 v cca and v ccd summed together.
wts701 - 72 - table 21. speaker driver specifications. parameter symbol test conditions spec unit min. typ. max. sp+/- output voltage (high gain setting) v sphg peak-to-peak, differential load = 150 ? 3.6 v sp+/- output load imp. (low gain) r splg 8 ? sp+/- output load imp. (high gain) r sphg 70 150 ? sp+/- output load cap. cs p 100 pf sp+/- output bias voltage (analog ground) v spag 1.2 v dc speaker output dc offset v spdco with auxin to speaker, auxin ac coupled to v ssa 100 mv dc power supply rejection ratio psrr measured with a 1 khz, 100 ma sine wave input at v cc and v cc pins -55 db frequency response (300-3400 hz) f r with 0tlp input to aux in, 6 db setting (12) -0.25 +0.25 db power output (low gain setting) p utlog differential load at 8 ? 23.5 mw rms
wts701 publication release date: may 2003 - 73 - revision 3.09 table 22. auxout parameters. parameter symbol test conditions spec unit min. typ. max. auxout ? maximum output swing v anaiut 5k ? load (ac coupled) 1.0 v minimum load impedance r l 5 k ? maximum load capacitance c l 100 pf auxout v bias 1.2 vdc table 23. volume control parameters. parameter symbol test conditions spec unit min. typ. max. output gain a out 8 steps of 4 db, referenced to output -28 to 0 db absolute gain auxin 1.0 khz 0tlp, 6 db gain setting measured differentially at sp+/- -0.5 +0.5 db
wts701 - 74 - 11. typical application circuit the following schematic diagrams are extracted from the wts-es701 evaluation board schematic. the evaluation system includes t he following basic clusters: wts701 processor cluster working wi th 3.3v, including an 8-ohm speaker, spi connector to the host pc via the pc parallel port. for more information about the evaluation system, please refer to the wts-es701 user?s guide. pad_spk- pad_fs pg 1,3 pad_rdy pad_spk+ pad_reset y2 xtal pad_xto pg 1 j2 mj-3536n 1 2 3 pad_mosi pg 1,3 j7 1 2 3 pad_miso pg 1,3 auxout u5 wts701 25 15 16 14 6 26 13 8 7 52 40 42 5 4 3 2 36 46 9 10 11 12 27 44 48 54 csb ssb sclk mosi miso rdy intb xti xto auxin attcap spk- vdx vfs vclk vssa1 vssa2 spk+ vssdn vssd vccd vccdn reset vssa3 vcca auxout pad_xto pad_xti r11 33k c18 10pf vccd pad_din pad_auxout pad_attcap u6 crystal socket 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 78 9 10 11 12 13 14 c23 .1uf pad_auxin j4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 c19 10pf r13 10k pad_bclk pad_sclk csb pad_xti j5 mj-3536n 1 2 3 vcca c17 .1uf pad_rdy pad_bclk pg 1,3 pad_auxout pg 1 c25 .1uf pad_reset pg 1,3 pad_rdy pg 1,3 pad_spk- pg 1 pad_attcap pad_auxout pad_intb gnda speaker vccd pad_auxin pad_mosi pad_din pg 1,3 vcca pad_fs c24 .1uf vccd c21 .1uf vccd pad_sclk pg 1,3 pad_spk+ pg 1 pad_xti pg 1 vccd pad_miso r9 33k pad_intb pg 1,3 c22 .1uf pad_intb pad_ssb pg 1,3 r12 33k + r8 10k auxin csb pg 1 vcca r10 33k c20 4.7uf j1 mj-3536n 1 2 3 pad_xto label pins of j4 with signal names. vccd vcca gnd pad_ssb pad_spk- pad_attcap pg 1 pad_auxin pg 1 pad_miso pad_spk+ c26 .1uf
wts701 publication release date: may 2003 - 75 - revision 3.09 12. package drawing and dimensions 56 l tsop(i) (14x20 mm)
wts701 - 76 - 13. ordering information for the latest product information, access winbond?s worldwide website at http://www.wi nbond-usa.com wts701__ __ /__ language e ? english m ? mandarin package type t ? tsop 56-leads voice f ? female m ? male
wts701 publication release date: may 2003 - 77 - revision 3.09 headquarters winbond electronics corporation america winbond electronics (shanghai) ltd. no. 4, creation rd. iii 2727 north first street, san jose, 27f, 299 yan an w. rd. shanghai, science-based industrial park, ca 95134, u.s.a.. 200336 china hsinchu, taiwan tel: 1-408-9436666 tel: 86-21-62365999 tel: 886-3-5770066 fax: 1- 408-5441798 fax: 86-21-62356998 fax: 886-3-5665577 http:// www.wi nbond-usa.com http://www.wi nbond.com.tw taipei office winbond electronics corporat ion japan winbond electronics (h.k.) ltd. 9f, no. 480, pueiguang rd 7f daini-ueno bldg, 3-7-18 unit 9-15, 22f, millennium city, neihu district, shinyokohama kohoky-ku, no. 378 kwun tong rd., taipei, 114, taiwan yokohama, 222-0033 kowloom, hong kong tel: 886-2-81777168 tel: 81-45-4781881 tel: 852-27513100 fax: 886-287153579 fax: 81-45-4781800 fax: 852-27552064 please note that all dataand specifications are subject to change without notice. all the trademarks of products and companies mentioned in this datasheet belong to t heir respective owners. this product incorporates superfl ash? technology licensed from sst. 14. version history version date page description 3.07 apr. 2002 1-73 initial issue 3.08 jun. 2002 1-73 improved package drawing, added illegal commands description, modified part number format 3.09 may 2003 all add crystal spec., descr iption of buffer length limit & undefined characters, consonant phoneme char acters (p & q), ^u3 and ^q control characters. the contents of this document are prov ided only as a guide for the applications of winbond products. winbond makes no representation or warrant ies with respect to the accuracy o r completeness of the contents of this publication and reserves the right to discontinue or make changes to specifications and produc t descriptions at any time without notice. no license, whethe r express or implied, to any intellect ual property or other right of winbond or others is granted by this publication. except as set forth in winbond's standard terms and conditions of sale, winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or inf ringement of any intellectual property. winbond products are not designed, intended, authoriz ed or warranted for use as components in systems or equipments intended for surgical implant ation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for ot her applications intended to support or sustain life. further, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property o r environmental in j ur y could occur.

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